In recent years, there have been tremendous interest in organic thin film transistors (OTFTs), which promise applications such as RFID tags and liquid crystal displays, because fabricating OTFTs using solution processes such as spin-coating and jet-printing represents a low-cost manufacturing option compared to conventional costly photolithography. A desirable gate dielectric for OTFTs should have a very low gate leakage current (pinhole free) and high capacitance. To achieve high device yield, a considerable dielectric thickness (e.g., >500 nm) is typically used to reduce pinhole density, thus gate leakage current to an acceptable level. To achieve high capacitance, on the other hand, a thin dielectric layer (e.g., <300 nm) is preferred, since solution processable polymeric gate dielectrics usually have low dielectric constants. Therefore, there is a need for processes to make a thin dielectric layer having both high device yield and low gate leakage. However, OTFTs with a thin gate dielectric typically have high leakage and low yield due to pinholes. Thus, there is a need addressed by embodiments of the present invention for new electronic devices and new electronic device fabrication methods where the deleterious effects of pinholes are reduced.
The following documents provide background information:
Takehiro, U.S. Pat. No. 7,176,071 B2.